Customize the Reference Design

Customize the Reference Design#

You can customize the reference design in several ways:

  1. Modify the IPs in the hardware platform using Vivado, then regenerate the platform. For details, see UG1701.

  2. Replace the VART-X pre-processing kernel with your own custom PL pre-processing kernel.

  3. Swap out the current program overlay for a different overlay. Where the new overlay adds AIE kernels that will run alongside Vitis AI inference, the AIE Array must be partitioned by column range; see Partitioning the AIE Array Across Multiple Workloads.

    The new overlay might result from either:

    • Adding new PL kernels and AIE kernels, or

    • Replacing existing PL kernels and AIE kernels

    Previously programmed PL/AIE kernel overlays can be overwritten using the fpgautil commands described in the Step 3: Program PL + AIE Overlay section.

  4. Integrate meta-vek385 and meta-vitis-ai layers into a custom Yocto project.

    You can copy the board-specific layer (meta-vek385) and the Vitis AI layer (meta-vitis-ai) into your Yocto project to integrate them with your existing Yocto build system.

    The paths for these layers are located at:

    Vitis-AI/versal_2ve/reference_design/vek385/rev-b/sw/yocto