Vitis AI System-Level Flow Overview

Vitis AI System-Level Flow Overview#

Reference Design Architecture

This section describes how an AMD Vitis™ AI application progresses from hardware design to accelerated deployment on a target board, with clear handoffs between roles and references to supporting documentation. Vitis AI model compilation can proceed independently of platform creation in Vitis and Vivado. Model compilation is targeted to a specific device; as long as the Vitis AI compiler supports that device, model and application developers can work in parallel with system developers using Vitis and Vivado.

Platform Selection and Preparation#

Vitis development begins by selecting the target device, either as a specific part or a board. This choice determines the hardware platform that underpins the bootable design and is later extended in Vitis to host the Vitis AI application. For AMD development boards, Vitis provides pre-built and validated base platforms to accelerate bring-up. For custom boards or designs, create the hardware platform in Vivado.

Vivado Development#

The Vivado developer creates a project for the selected device or custom board and generates an extensible XSA. Comprehensive Vivado documentation is available here: Vivado Documentation.

Platform Integration in Vitis#

The Vitis system developer integrates PL pre- and post-processing IP, manages data movement, and links the AI pipeline with the extensible XSA to produce a fixed XSA. For guidance on custom platform setup, including hardware interfaces, clocks, interrupts, and NoC memory - refer to UG1701, Building Custom Platforms. Iterative refinement between Vitis and Vivado is supported through the Vitis Export to Vivado flow to regenerate the latest extensible XSA as needed.

System Software Stack#

The system software developer uses the boot.pdi from Vivado with Yocto to create a bootable Linux image, then adds application-specific libraries and runtime drivers. An end-to-end example is available in the AMD Embedded Development Framework (EDF).

Model and Application Development#

Vitis AI model compilation is independent of platform creation in Vitis and Vivado. Model compilation is targeted to a specific device; as long as the Vitis AI compiler supports that device, model and application developers can work in parallel with system developers using Vitis and Vivado. The Vitis AI model developer compiles the ONNX model into a cached model ELF. The Vitis AI application developer implements the application targeting the prepared platform. Deployment to the board for inference includes the following artifacts: boot.bin, the device tree and runtime drivers, the application ELF, the cached model ELF, and any required PL/AIE overlays.

Reference Design#

An example system reference design is provided in the Integrated System Reference Design source, available from amd/Vitis-AI.

Note

  • By default, all source paths and pre-built images in this document are configured for the VEK385 rev B target board, which should be used as the primary option.

  • If only a VEK385 rev A target board is available, VEK385 rev A sources and pre-built binaries are also included in this Vitis AI 6.2 package as a fallback option.

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